MP1763C – Anritsu Pattern Generators
12.50Gbps (Max. Data Rate)
The MP1763C is used in combination with the MP1764C or MP1764D Error Detector for 12.5G BER testing. The amplitude of the clock and data signals can be varied from 0.25 to 2 Vp-p while the offset can be adjusted to within ±2 V so that the amplitude and the offset margin can be measured. The clock has a variable delay function so that time dependent characteristics or phase margins of the input clock and data can be measured. An M-series pseudorandom pattern representative of actual conditions or a programmable pattern can be selected as cell data. Features: High quality waveform Wide frequency range covers STM 0/STS1 to 10 GbE, STM64/STS192, OUT-2, and 4.25G Fibre Channel Low FM/PM-noise clock generator 1/8 parallel output standard, with available options for either 1/4 parallel output or 1/4 differential output 8 Mbit programmable pattern corresponding to six frames of STM-64/ STS-192 Complementary outputs of both data and clock The amplitudes and offsets of all 8 data outputs that have 1/8 speed of fundamental clock signal can be set

Specifications

Max. Data Rate

12.50Gbps

Channels

3

Max. PRBS Pattern

31

Pattern Depth

N/A

More Details

12.5G Pulse Pattern Generator