ME7760B – Anritsu Bit Error Rate Testers
43.50Gbps (Max. Data Rate)
The Anritsu ME7760B 43.5 Gbit/s BERT System†is composed of five hardware elements plus software that runs on a GPIB-connected PC. Each system element is described on a separate product page: click on the links below to see these 43.5G BER products. ME7760B is the standard system, and ME7760A is a lower-cost version. The ME7780A 48G BER Test Solution is a similar system available for higher rate signals.
The signal output side consists of a 50G or 65G signal generator (MG3690B Series) for generating the clock signal, a pulse pattern generator (MP1775A) for generating four channels of SDH/SONET patterns, and the MP1803A 4:1 multiplexer (MP1801A for the ME7760A system) for multiplexing these signals into a 43.5 Gbps signal.
The receive side consists of the MP1804A 1:4 demultiplexer (MP1802A for the ME7760A system) for splitting the 43.5 Gbps signal into four channels and an error detector (MP1776A) for measuring the error rate of the four channels.
The pulse pattern generator (MP1775A) on the send side and the error detector (MP1776A) on the receive side are connected by GPIB cables to a PC running the SDH/SONET pattern editing software (MX177601A) used to edit the pattern data. The MP1775A Pulse Pattern Generator can simultaneously generate a PRBS*5 pattern of up to 12.5 Gbps as well as four channels of SDH/SONET frame patterns of 8 Mbit each. When this system is used in combination with the 43.5G MUX, the four signal channels can be multiplexed to generate a 43.5 Gbps PRBS pattern and a SDH/SONET frame pattern for up to 6 frames.
Excellent data output waveforms, low jitter, and fast rise/fall times make the ME7760A/B an ideal BER test solution for verifying and characterizing electrical/optical systems, modules, and devices supporting FEC, non-FEC, and Super FEC rates from 25 Gbps to 43.5 Gbps.† User flexibility is built into the ME7760A/B system to effectively optimize the use of all of its components. All instruments making up this BERT system can also be used standalone or in different combinations based on test requirements, increasing the value of the capital investment.
Max. Data Rate
Max. Clock Rate
32 Mbits pattern memory
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